Address Space, Cacheability. MTRR's, and the BIOS. Beginning with the introduction of the Pentium Pro, microprocessors in the IA-32 family provide a 36-bit address bus. This enables them to support up to 64 GB of physical memory. All or portions of this physical memory may be cached in various ways in order to enhance performance. For example, one region of the address space may be designated as write-through, another may be designated as write-back, while still others may be designated as write-protected, write-combining or uncacheable. Assigning such cacheability characteristics to regions of the address space may be achieved by writing appropriate values into one or more pairs of memory type range registers (“MTRR's”). In most IA-32 computer systems, firmware known as the basic input-output system (“BIOS”) begins executing prior to loading the operating system and configures certain resources within the computer including the MTRR's. Thus, it is generally a BIOS function to define caching behavior for regions within physical memory by programming the MTRR's.
Memory-Mapped IO. IA-32 processors permit applications to access input/output (“IO”) ports in either of two ways: through a separate IO address space or through the physical memory address space. The latter approach is commonly referred to as “memory-mapped IO.” Accessing IO ports through the separate IO address space is achieved using a special set of IO instructions. Accessing IO ports through the physical memory address space, on the other hand, has the advantage that any of the processor's instructions that reference memory may be used to interact with IO devices.
Memory-mapped IO does present complications, however. One such complication arises in the context of cacheability: When controlling IO devices, it is usually important that IO operations be executed in precisely the order in which they are programmed to occur. Consequently, it is generally recommended that the portion of the physical address space to be used for memory-mapped IO should be designated as uncacheable. This is so because designating a memory-mapped IO region of the physical address space as uncacheable insures that reads from and writes to locations in the uncacheable region are carried out in program order.
Chipsets, the 4 GB Boundary and the Top of Lower Memory. Accesses to main memory by the CPU and other devices within a computer are generally handled by a memory controller chip—one of several chips commonly known as the “chipset.” A chipset provides bus interface, data path, instruction caching and similar functions on the motherboard. The BIOS must configure the chipset at boot time with information about where main memory is located. If memory-mapped IO is in use, then the chipset must have information not only about where the actual main memory will be located, but also about where the memory-mapped IO region will be located within the physical memory address space.
Intel E7501 and similar chipsets for IA-32 platforms are designed to assume that certain devices will always be mapped into the peripheral component interconnect (“PCI”) memory address range—that is, the address range beginning at 4 GB and extending downward far enough to include a certain size of addresses. Specifically, they assume that the advanced programmable interrupt controller (“APIC”) addresses, the hub interface addresses, and any memory-mapped IO addresses will reside in this range. For purposes of this document, therefore, references made to “PCI memory,” the “PCI memory address range,” or the “PCI range” shall mean the range of addresses beginning at 4 GB (actually 4096 MB) and extending downward far enough to include the size of the APIC addresses, the hub interfaces addresses, and the memory-mapped IO addresses.
Configuration of these chipsets requires among other things that the BIOS write appropriate values into the top of lower memory (“TOLM”) register and into the DRAM row boundary 7 (“DRB7”) register. The TOLM register is designed to contain the maximum address below 4 GB that should be treated as main memory. The DRB7 register is designed to contain the maximum address in the machine that should be treated as main memory. Thus, for machines having less physical memory than 4 GB minus the minimum size required for the PCI memory address range, the TOLM and DRB7 registers will contain the same value. But for machines having more memory than that, the physical memory must be split because the PCI memory address range may not be moved. In such machines, there will be one region of physical memory located below the PCI range, and another region of physical memory located above the PCI range. The TOLM register will indicate the highest address within the first range. The DRB7 register will indicate the highest address within the second range.
Prior Art Recommendation for Setting TOLM. In reference to setting the value to be contained by the TOLM register, the E7501 chipset data sheet contains the following recommendation: “Configuration software should set this value to either the maximum amount of memory in the system or to the minimum address allocated for PCI memory, whichever is smaller.” In other words, the prior art recommendation for setting TOLM is to choose a value that will maximize the amount of physical memory located below the PCI range, regardless of the amount of physical memory available on the machine.